1. Field of the Invention
The invention relates to improved programmable logic devices. More particularly this invention relates to programmable logic devices that provide more efficient configuration of block memories
2. Description of the Related Art
Programmable logic devices include configuration memory cells, configuration control elements and a matrix of logic blocks, IO blocks and block RAMs. Field programmable gate arrays (FPGAs) are one of the most commonly used programmable logic devices. FIG. 1 shows the block diagram of a typical FPGA. The FPGA includes vertical shift register (VSR) 13 and select register HFF 11 both connected to a control unit 14 and core 12 comprising a plurality of routing lines and an array of memory latches. The control unit 14 has input data, control and status busses to control the operation of the FPGA. To configure the core of the FPGA a data frame is loaded into the VSR 13 and the control unit enables one select line of the select register HFF 11 to shift the column of data from VSR 13 to one column of the core.
FIG. 2 shows the memory latch. A memory latch comprises cross-coupled inverters 22 having transistors 23, 24 connected to them for reading and writing the data. The control terminals of the transistors enable the read or write operation into/from latch.
Block memories are often provided in FPGAs for storing data. FIG. 3 shows an embodiment of the FPGA with block memories 33, 31. The block memories are generally arranged in columns around the array of PLB and routing resources. The figure shows only two columns of the block memory, however there can be more columns of block memories.
FIG. 3 show an FPGA with block memories having a core 32, which is made out of a programmable logic block (PLB) 37 and routing resources 38, 39. The routing resources also interact with the memory. The data in the frames is loaded in the VSR 34, the appropriate line is selected using HFF 36 and the data is transferred from VSR 34 to the corresponding latches. The control unit 35 controls the operation of VSR 34 and HFF 36. The control unit 35 is responsible for accepting the data from the external environment, verifying the data and then loading the data using control signals. Block memories 33 are used as Random Access Memories (RAM) in which the data is loaded during runtime in accordance with the functionality implemented in FPGA. The FPGAs have additional controls (not shown) to control the operation of the block memories as RAMs.
The block memories can also be used as Read Only Memories (ROMs) to augment the configuration memory (or PLB) of the FPGA.
U.S. Pat. No. 5,787,007 describes a scheme for configuring block memories, utilizing the reconfiguration option of the FPGA. In this particular scheme the FPGA is first configured as a RAM loader circuit in which the data is loaded into the RAM, after which it is reconfigured for other desired functions. The control blocks, address counters, and data shift registers for block memory loading are programmed using the block memory. The major disadvantage of this scheme is the requirement of reconfiguration of the system, which results in increased total configuration time. Also the control block of such a system is significantly more complex because it is required to detect the completion of the initial configuration, after which it is required to perform the configuration of the internal memories followed by the reinitialization for the desired logic device.